Semiconductor device and method of manufacturing the semiconductor device

ABSTRACT

Resistance of a gate electrode is reduced in a split gate MONOS memory configured by a fin FET. A memory gate electrode of a split gate MONOS memory is formed of a first polysilicon film, a metal film, and a second polysilicon film formed in order on a fin. A trench between fins adjacent to each other in a lateral direction of the fins is filled with a stacked film including the first polysilicon film, the metal film, and the second polysilicon instead of the first polysilicon film only.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2016-191808 filed onSep. 29, 2016 including the specification, drawings and abstract isincorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to a semiconductor device and a method ofmanufacturing the semiconductor device, and more particularly relates toa technique effectively applied to a semiconductor device including afin transistor.

A fin field effect transistor is known as a field effect transistor thatoperates at high speed, and allows a reduction in leakage current, powerconsumption, and size. The fin field effect transistor (FINFET) is, forexample, a semiconductor element that has a channel layer including apattern of a plate-like (wall-like) semiconductor layer protruding abovea substrate, and has a gate electrode formed so as to straddle thepattern.

The electrically erasable and programmable read only memory (EEPROM) iswidely used as an electrically writable and erasable, nonvolatilesemiconductor memory device. Such memory devices typified by a currentlywidely used flash memory each have a conductive floating gate electrodesurrounded by an oxide film or a trapping insulating film below a gateelectrode of a MISFET, and a charge storage state in the floating gateor the trapping insulating film is used as memory information, and isread as a threshold of the transistor. The trapping insulating filmrefers to a charge-storable insulating film, and includes, for example,a silicon nitride film. Electron charges are injected or emittedinto/from such a charge storage region to shift the threshold of theMISFET so that the MISFET operates as a memory element. Such a flashmemory includes a split gate cell using ametal-oxide-nitride-oxide-semiconductor (MONOS) film.

Japanese Unexamined Patent Application Publication (Translation of PCTApplication) No. 2013-504221 describes a split gate flash memory havinga FINFET.

Japanese Unexamined Patent Application Publication No. 2016-51735describes a split gate MONOS memory, in which a memory gate electrode isformed of a polysilicon film and a metal film on the polysilicon film.

SUMMARY

A reduction in resistance of a gate electrode is a typical issue ofFETs. The same point is valid with regard to a split gate MONOS memory.In an existing method for reducing resistance of a control gateelectrode or a memory gate electrode, such a gate electrode is formed ofa metal film or a stacked film including a silicon film and a metal filmon the silicon film. However, when the entire memory gate electrode isformed of a metal film, an insulating film between a trapping insulatingfilm (charge storage film) and the memory gate electrode react with themetal film, which deteriorates a charge retention characteristic of thetrapping insulating film.

Other objects and novel features will be clarified from the descriptionof this specification and the accompanying drawings.

A typical one of embodiments disclosed in this application is brieflysummarized as follows.

In a semiconductor device of one embodiment, a memory gate electrode ofa memory cell provided over each of a plurality of fins is formed of asemiconductor film and a metal film formed in order on the fin, and aspace between the fins is filled with the semiconductor film and themetal film.

In a method of manufacturing a semiconductor device according to oneembodiment, a memory gate electrode of a memory cell provided on each ofa plurality of fins is formed of a semiconductor film and a metal filmformed in order on the fin, and a space between the fins is filled withthe semiconductor film and the metal film.

According to one embodiment disclosed in the present application,performance of a semiconductor device can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram illustrating a layout configuration of asemiconductor chip of a first embodiment of the invention.

FIG. 2 is a plan view illustrating a semiconductor device of the firstembodiment of the invention.

FIG. 3 is a perspective view illustrating the semiconductor device ofthe first embodiment of the invention.

FIG. 4 is a sectional view illustrating the semiconductor device of thefirst embodiment of the invention.

FIG. 5 is a plan view illustrating the semiconductor device of the firstembodiment of the invention.

FIG. 6 is a sectional view along a line C-C in FIG. 5.

FIG. 7 is a sectional view of the semiconductor device of the firstembodiment of the invention during a manufacturing process of thesemiconductor device.

FIG. 8 is a sectional view of the semiconductor device during themanufacturing process following FIG. 7.

FIG. 9 is a sectional view of the semiconductor device during themanufacturing process following FIG. 8.

FIG. 10 is a sectional view of the semiconductor device during themanufacturing process following FIG. 9.

FIG. 11 is a sectional view of the semiconductor device during themanufacturing process following FIG. 10.

FIG. 12 is a sectional view of the semiconductor device during themanufacturing process following FIG. 11.

FIG. 13 is a sectional view of the semiconductor device during themanufacturing process following FIG. 12.

FIG. 14 is a sectional view of the semiconductor device during themanufacturing process following FIG. 13.

FIG. 15 is a sectional view of the semiconductor device during themanufacturing process following FIG. 14.

FIG. 16 is a sectional view of the semiconductor device during themanufacturing process following FIG. 15.

FIG. 17 is a sectional view of the semiconductor device during themanufacturing process following FIG. 16.

FIG. 18 is a sectional view of the semiconductor device during themanufacturing process following FIG. 17.

FIG. 19 is a sectional view of the semiconductor device during themanufacturing process following FIG. 18.

FIG. 20 is a sectional view of the semiconductor device during themanufacturing process following FIG. 19.

FIG. 21 is a sectional view of the semiconductor device during themanufacturing process following FIG. 20.

FIG. 22 is a sectional view of the semiconductor device during themanufacturing process following FIG. 21.

FIG. 23 is a sectional view of the semiconductor device during themanufacturing process following FIG. 22.

FIG. 24 is a sectional view of the semiconductor device during themanufacturing process following FIG. 23.

FIG. 25 is an equivalent circuit diagram of a memory cell of anonvolatile memory.

FIG. 26 is a table showing an exemplary voltage application condition toeach part of a selected memory cell in “write”, “erase”, and “read”.

FIG. 27 is a sectional view of a semiconductor device of a modificationof the first embodiment of the invention during a manufacturing processof the semiconductor device.

FIG. 28 is a sectional view of a semiconductor device of a secondembodiment of the invention during a manufacturing process of thesemiconductor device.

FIG. 29 is a sectional view of the semiconductor device during themanufacturing process following FIG. 28.

FIG. 30 is a sectional view of the semiconductor device during themanufacturing process following FIG. 29.

FIG. 31 is a sectional view of a semiconductor device of a thirdembodiment of the invention during a manufacturing process of thesemiconductor device.

FIG. 32 is a sectional view of the semiconductor device during themanufacturing process following FIG. 31.

FIG. 33 is a sectional view of a semiconductor device of a comparativeexample during a manufacturing process of the semiconductor device.

FIG. 34 is a sectional view of a semiconductor device of anothercomparative example during a manufacturing process of the semiconductordevice.

FIG. 35 is a sectional view of a semiconductor device of anothercomparative example during a manufacturing process of the semiconductordevice.

DETAILED DESCRIPTION

Although each of the following embodiments may be dividedly described ina plurality of sections or embodiments for convenience as necessary,they are not unrelated to one another except for the particularlydefined case, and are in a relationship where one is a modification,details, supplementary explanation, or the like of part or all ofanother one. In each of the following embodiments, when the number ofelements and the like (including the number, a numerical value, amount,and a range) is mentioned, the number is not limited to a specifiednumber except for the particularly defined case and for the case wherethe number is principally clearly limited to the mentioned number. Inother words, the number may be not less than or not more than thementioned number. Furthermore, it will be appreciated that in each ofthe following embodiments, a constitutional element (including anelement step etc.) of the embodiment is not necessarily indispensableexcept for the particularly defined case and for the case where theconstitutional element is considered to be indispensable in principle.Similarly, in each of the following embodiments, when a shape of aconstitutional element, a positional relationship, and the like aredescribed, any configuration substantially closely related to or similarto such a shape or the like should be included except for theparticularly defined case and for the case where such a configuration isconsidered to be not included in principle. The same point is valid withregard to each of the numerical value and the range.

Hereinafter, some embodiments will be described in detail with referenceto the accompanying drawings. In all drawings for explaining theembodiments, components having the same function are designated by thesame numeral, and duplicated description is omitted. In the followingembodiments, the same or similar portion is not repeatedly described inprinciple except for a particularly required case.

First Embodiment Exemplary Layout Configuration of Semiconductor Chip

A semiconductor device having a nonvolatile memory of a first embodimentis now described with reference to some drawings. First, a layoutconfiguration of a semiconductor device (semiconductor chip) having asystem including a nonvolatile memory is described. FIG. 1 is aschematic diagram illustrating an exemplary layout configuration of asemiconductor chip CHP of the first embodiment. In FIG. 1, thesemiconductor chip CHP includes a central processing unit (CPU) CC1, arandom access memory (RAM) CC2, and an analog circuit CC3. Thesemiconductor chip CHP further includes an electrically erasableprogrammable read only memory (EEPROM) CC4, a flash memory CC5, and aninput/output (I/O) circuit CC6, and thus configures a semiconductordevice.

The CPU (circuit) CC1, which may be called a central processing unit,reads and decodes instructions from a memory device, and performsvarious types of arithmetic operation and control based on theinstructions.

The RAM (circuit) CC2 is a memory, from which memory information can berandomly read, i.e., randomly stored memory information can be read, andinto which memory information can be newly written, and is also calledrandom-access memory. A static RAM (SRAM) including a static circuit isused as the RAM.

The analog circuit CC3 is a circuit that processes a voltage signal anda current signal, which each vary continuously over time, i.e.,processes analog signals, and includes, for example, an amplifiercircuit, a conversion circuit, a modulation circuit, an oscillationcircuit, and a power supply circuit.

The EEPROM CC4 and the flash memory CC5 are each one of nonvolatilememories, which allows memory information to be electrically rewrittenin write operation and erase operation, and are each also calledelectrically erasable programmable read only memory. A memory cell ofthe EEPROM CC4 or the flash memory CC5 is comprised of, for example, ametal oxide nitride oxide semiconductor (MONOS) transistor or a metalnitride oxide semiconductor (MNOS) transistor for memory. For example,the EEPROM CC4 and the flash memory CC5 are different from each other inthat the EEPROM CC4 is a nonvolatile memory that can be erased in byteswhile the flash memory CC5 is a nonvolatile memory that can be erased inword lines. In general, the flash memory CC5 stores programs for varioustypes of processing to be executed by the CPU CC1. On the other hand,the EEPROM CC4 stores various data to be rewritten at a high frequency.The EEPROM CC4 or the flash memory CC5 includes a memory cell arrayincluding a plurality of nonvolatile memory cells arranged in a matrix,and further includes an address buffer, a row decoder, a column decoder,a verify sense amplifier circuit, a sense amplifier circuit, a writecircuit, and the like.

The I/O circuit CC6, which is an input/output circuit, outputs data fromwithin the semiconductor chip CHP to an external device coupled to thesemiconductor chip CHP, or receives data from the external devicecoupled to the semiconductor chip CHP and sends the data into thesemiconductor chip, for example.

The semiconductor device of the first embodiment has a memory cellregion and a logic circuit region. The memory cell region has a memorycell array including a plurality of nonvolatile memory cells arranged ina matrix. The logic circuit region has the CPU CC1, a RAM CC2, theanalog circuit CC3, the I/O circuit CC6, an address buffer for theEEPROM CC4 or the flash memory CC5, a row decoder, a column decoder, theverify sense amplifier circuit, and the sense amplifier circuit or thewrite circuit.

Structure of Semiconductor Device

A structure of the semiconductor device of the first embodiment is nowdescribed with reference to FIGS. 2 to 6. FIG. 2 is a plan view of thesemiconductor device of the first embodiment. FIG. 3 is a perspectiveview of the semiconductor device of the first embodiment. FIGS. 4 and 6are each a sectional view of the semiconductor device of the firstembodiment. FIG. 5 is a plan view of the semiconductor device of thefirst embodiment. FIG. 4 shows respective sections along a line A-A anda line B-B in FIG. 2. FIG. 6 shows a section along a line C-C in FIG. 5.FIG. 3 omits an interlayer insulating film, a silicide layer, and aninterconnection on a semiconductor substrate, and further omits sourceand drain regions and a well in the semiconductor substrate.

FIG. 2 shows a plan view of the memory cell array. A plurality of memorycells MC formed in the memory cell array are provided, for example, inthe flash memory CC5 in FIG. 1. Hereinafter, the region having thememory cells is called memory cell region.

A plurality of fins FA extending in an X direction are disposed at equalintervals in a Y direction in the memory cell region 1A. The X directionand the Y direction are each a direction along the main surface of asemiconductor substrate SB, and the X direction is orthogonal to the Ydirection. Each fin FA is, for example, a rectangular parallelepipedprotrusion (convex portion) selectively protruding from the main surfaceof the semiconductor substrate SB, and has a wall-like (plate-like)shape. The fin FA is a part of the semiconductor substrate SB, and actsas an active region of the semiconductor substrate SB. A space betweenthe adjacent fins FA is filled with an element isolation film EI, andeach fin FA is surrounded by the element isolation film EI in planarview. The fin FA acts as an active region for forming the memory cellMC. The semiconductor substrate SB is made of, for example, p-typesingle crystal silicon having a specific resistance of about 1 to 10Ωcm.

The lower end portion of the fin FA is surrounded by the elementisolation film EI covering the main surface of the semiconductorsubstrate SB. However, a part of the fin FA protrudes above the elementisolation film EI. In other words, a region between the adjacent fins isnot entirely filled with the element isolation film EI.

A plurality of control gate electrodes CG and a plurality of memory gateelectrodes MG extending in the Y direction are disposed on the fins FA.A drain region MD on a side close to the control gate electrode CG and asource region MS on a side close to the memory gate electrode areprovided on the top of the fin FA so as to sandwich the control gateelectrode CG and the memory gate electrode MG. Specifically, one controlgate electrode CG and one memory gate electrode MG adjacent to eachother in the X direction are located between the source region MS andthe drain region MD.

The drain region MD and the source region MS are each an n-typesemiconductor region. The drain region MD is provided between twocontrol gate electrodes CG adjacent to each other in the X direction,and the source region MS is provided between two memory gate electrodesMG adjacent to each other in the X direction. The memory cell MC is anonvolatile memory element having the control gate electrode CG, thememory gate electrode MG, the drain region MD, and the source region MS.Hereinafter, the source region MS and the drain region MD configuringone memory cell MC may be referred to as source/drain region.

Two memory cells MC adjacent to each other in the X direction share thedrain region MD or the source region MS. The two memory cells MC sharingthe drain region MD are axisymmetric in the X direction with the drainregion MD extending in the Y direction as an axis. The two memory cellsMC sharing the source region MS are axisymmetric in the X direction withthe source region MS extending in the Y direction as an axis.

Each fin FA has a plurality of memory cells MC arranged in the Xdirection. The drain region MD of each memory cell MC is electricallycoupled to a source line SL including an interconnection MW extending inthe X direction via a plug (contact plug) PG formed in a contact holepenetrating through an undepicted interlayer insulating film formed onthe memory cell MC. The source regions MS of the memory cells MCarranged in the Y direction are electrically coupled to a bit line BLincluding an interconnection MW extending in the Y direction.

The fin FA is, for example, a rectangular parallelepiped protrusionprotruding from the main surface of the semiconductor substrate SB in adirection perpendicular to the main surface. The fin FA may notnecessarily have a rectangular parallelepiped shape, but may have arectangular shape having rounded corners in sectional view in a shortside direction. Although each side face of the fin FA may beperpendicular to the main surface of the semiconductor substrate SB, theside face may have an inclination angle close to the vertical. That is,the sectional shape of the fin FA is a rectangular parallelepiped or atrapezoid. In this exemplary case, the side faces of the fin FA are eachobliquely inclined with respect to the main surface of the semiconductorsubstrate SB.

As illustrated in FIG. 2, a direction, in which the fins FA extend inplanar view, is the long side direction of each fin, and the directionorthogonal to the long side direction is the short side direction of thefin. That is, length of the fin is larger than width thereof. The fin FAmay have any shape as long as the fin includes a protrusion having alength, a width, and a height. For example, the fin may have ameandering layout in planar view.

FIG. 3 shows two memory cells MC formed side by side on one fin FA, inwhich the control gate electrode CG, the memory gate electrode MG, andthe ONO film ON of the memory cell MC on the left side of the drawingare shown with their cross sections directly over the element isolationfilm EI, and the control gate electrode CG, the memory gate electrodeMG, and the ONO film ON of the memory cell MC on the right side of thedrawing are shown with their cross sections directly over the fin FA. Amemory cell MC is provided above the fin FA configuring thesemiconductor substrate SB in the memory cell region. As illustrated inFIG. 3, the control gate electrode CG and the memory gate electrode MGextend in the Y direction so as to stride over the fin FA.

FIG. 4 shows, side by side, across section of a semiconductor elementalong a line A-A in FIG. 2 and a cross section of the semiconductorelement along a line B-B in FIG. 2. Specifically, a cross section alonga gate length direction (X direction) of a FINFET configuring the memorycell MC is shown on the left side of FIG. 4, and a cross section, whichincludes two fins FA, along a gate width direction (Y direction) of theFINFET configuring the memory cell MC is shown on the right side of FIG.4. The cross section shown on the right side of FIG. 4 includes thememory gate electrode MG configuring the memory cell MC. Although aplurality of elements are arranged on one fin FA, only one memory cellMC is shown on the fin FA in FIG. 4. Furthermore, FIG. 4 shows the oxidenitride oxide (ONO) film ON having a stacked structure as one insulatingfilm without separately showing the insulating films forming the ONOfilm ON.

As illustrated in FIGS. 3 and 4, a plurality of protrusions as part ofthe semiconductor substrate SB are arranged in the Y direction over thesemiconductor substrate SB. The side faces of each fin FA are partiallysurrounded by the element isolation film EI formed on the main surfaceof the semiconductor substrate SB. The element isolation film EI isembedded in a region between the adjacent fins FA. However, the elementisolation film EI fills only part of the region between the adjacentfins FA, and upper ends of the fins FA protrude above the elementisolation film EI. That is, the fins are isolated from one another bythe element isolation film EI. As illustrated in FIG. 4, a p-type wellPW being a p-type semiconductor region is provided in the fin FA fromthe top to the lower part of the fin FA.

The control gate electrode CG is provided on the top and the side facesof the fin FA and on the element isolation film EI with a gateinsulating film in between, and the memory gate electrode MG is providedin a region adjacent to the control gate electrode CG with an ONO filmON in between in the long side direction (X direction) of the fin FA.The ONO film ON is interposed between the control gate electrode CG andthe memory gate electrode MG, and the control gate electrode CG iselectrically isolated from the memory gate electrode MG by the ONO filmON. The ONO film ON is interposed between the memory gate electrode MGand the top of the fin FA. The insulating film ON is continuouslyprovided so as to cover the side faces and the bottom of the memory gateelectrode MG. Hence, the ONO film ON has an L-shaped section along thegate length direction as illustrated in FIG. 4.

The gate insulating film includes a stacked film of a thermal oxide film(silicon oxide film, insulating film IF3) formed by thermally oxidizingthe main surface and the side faces of the fin FA that is a protrusionof the semiconductor substrate SB made of silicon and a high dielectricconstant film (high dielectric film) HK, and has a thickness of 2.5 nm,for example. The insulating film IF3 forming the gate insulating filmhas a thickness of, for example, 1 nm, and the high dielectric constantfilm HK, which is provided on the insulating film IF3 and alsoconfigures the gate insulating film, has a thickness of 1.5 nm, forexample. The high dielectric constant film HK is an insulating filmincluding a HfO film, a HfON film, or a HfSiON film, and has adielectric constant higher than each of silicon oxide and siliconnitride.

The entire insulating film IF3 is provided along the surface of the finFA. That is, the insulating film IF3 is formed so as to cover the bottomof the control gate electrode CG. On the other hand, the high dielectricconstant film HK is provided so as to cover the bottom and the sidefaces of the control gate electrode CG.

The ONO film ON includes a silicon oxide film X1 including a thermaloxide film (silicon oxide film) 4 nm in thickness formed by thermallyoxidizing the main surface and the side faces of the fin FA that is theprotrusion of the semiconductor substrate SB made of silicon, a siliconnitride film NF formed on the silicon oxide film X1, and a silicon oxidefilm X2 formed on the silicon nitride film NF. The silicon nitride filmNF acts as a charge storage part (charge storage film, charge storagelayer) of the memory cell MC. The silicon nitride film has a thicknessof, for example, 7 nm, and the silicon oxide film X2 has a thickness of,for example, 9 nm.

That is, the ONO film ON has a stacked structure including the siliconoxide film X1, the silicon nitride film NF, and the silicon oxide filmX2, which are stacked in order from two sides, i.e., a side close to thetop of the fin FA and a side close to the side face of the control gateelectrode CG. The thickness of the ONO film ON is larger than thethickness of the gate insulating film under the control gate electrodeCG, and is 20 nm, for example. A silicon oxynitride film may be formedas the film X2 in place of the silicon oxide film X2.

The control gate electrode CG extends in the short side direction (Ydirection) of the fin FA, and is provided adjacent to the top and theside faces of the fin FA and the top of the element isolation film EIwith the gate insulating film in between. Similarly, the memory gateelectrode MG extends in the short side direction of the fin FA, and isprovided adjacent to the top and the side face of the fin FA and the topof the element isolation film EI with the ONO film ON in between. Thatis, the gate insulating film and the control gate electrode CGcompletely fill a trench between the fins FA adjacent to each other inthe short side direction of the fin FA. In addition, the ONO film ON andthe memory gate electrode MG completely fill a trench between the finsFA adjacent to each other in the short side direction of the fin FA. Thetops of the memory gate electrode MG and the ONO film ON are eachcovered with an insulating film IF5 that extends in the Y direction aswith the memory gate electrode MG. The insulating film IF5 includes, forexample, a silicon nitride film.

Each side face of a pattern including the control gate electrode CG, thememory gate electrode MG, the ONO film ON, and the insulating film IF5is covered with a sidewall (sidewall spacer) SW. The sidewall SW has astacked structure of a silicon nitride film and a silicon oxide film,for example. In the drawing, however, the sidewall SW is shown as onefilm, i.e., the silicon nitride film and the silicon oxide film are notseparately shown.

As illustrated in FIG. 4, a pair of a source region and a drain regionare provided on the top of the fin FA so as to sandwich the top of thefin FA directly below the pattern including the control gate electrodeCG and the memory gate electrode MG. Each of the source and drainregions has an extension region EX as an n⁻-type semiconductor regionand a diffusion region D1 as an n⁺-type semiconductor region. Theextension region EX and the diffusion region D1 are each a semiconductorregion formed by introducing an n-type impurity (for example, phosphorus(P) or arsenic (As)) into the fin FA.

The diffusion region D1 has a high impurity concentration compared withthe extension region EX. The extension region EX may have a depth deeperor shallower than the diffusion region D1. The extension region EX is incontact with the diffusion region D1 in each of the source and drainregions, and the extension region EX is located in the top of the fin FAdirectly below the pattern, i.e., located on a side close to a channelregion compared with the diffusion region D1.

The drain region is adjacent to the fin FA directly below the controlgate electrode CG, and the source region is adjacent to the fin FAdirectly below the memory gate electrode MG. That is, the source/drainregion sandwiches the pattern including the control gate electrode CGand the memory gate electrode MG in planar view, and the drain region islocated on a side close to the control gate electrode CG, and the sourceregion is located on a side close to the memory gate electrode MG. Inother words, the drain region is adjacent to the control gate electrodeCG while the source region is adjacent to the memory gate electrode MGin planar view.

In this way, the source/drain region, which has a structure includingthe extension region EX having a low impurity concentration and thediffusion region D1 having a high impurity concentration, i.e., alightly doped drain (LDD) structure, is formed, thereby it is possibleto improve short channel characteristics of the transistor having such asource/drain region. The source region of that source/drain regioncorresponds to the source region MS shown in FIG. 2, and the drainregion thereof corresponds to the drain region MD shown in FIG. 2.

A silicide layer S1 is provided on a surface of each of the sourceregion and the drain region exposed from the pattern including thecontrol gate electrode CG, the memory gate electrode MG, and thesidewall SW, i.e., on the surface of the diffusion region D1. Thesilicide layer S1 is made of, for example, nickel silicide (NiSi).

An interlayer insulating film IL1 including, for example, a siliconoxide film is provided on the fin FA and the element isolation film EI.The interlayer insulating film IL1 covers the fin FA, the elementisolation film EI, and the silicide layer S1, and the top of theinterlayer insulating film IL1 is planarized at a height substantiallyequal to the height of the top of each of the control gate electrode CG,the memory gate electrode MG, and the sidewall SW. An interlayerinsulating film IL2 covering the tops of the control gate electrode CG,the memory gate electrode MG, and the sidewall SW is formed on theinterlayer insulating film IL1. The top of the interlayer insulatingfilm IL2 is planarized. The interlayer insulating film IL2 includes, forexample, a silicon oxide film.

A plurality of interconnections MW are provided on the interlayerinsulating film IL2, and each interconnection MW is electrically coupledto the source region or the drain region of the memory cell MC via aplug PG provided in a contact hole penetrating through the interlayerinsulating films IL1 and IL2. Specifically, the bottom of the plug PG isdirectly in contact with the top of the silicide layer S1, and the plugPG is electrically coupled to the source region or the drain region viathe silicide layer S1. The silicide layer S1 reduces a couplingresistance between the plug PG as a coupling part including a metal filmmainly containing, for example, tungsten (W) and the source/drain regionin the fin FA made of semiconductor.

In an undepicted power feeding region for the control gate electrode CG,a plug is coupled to the top of the control gate electrode CG. In apower feeding region (see FIGS. 5 and 6) for the memory gate electrodeMG, the plug PG is coupled to the top of the memory gate electrode MG.

The memory cell MC is a nonvolatile memory element including the controlgate electrode CG, the memory gate electrode MG, the drain region, andthe source region. The control gate electrode CG and the source/drainregion configure a control transistor, and the memory gate electrode MGand the source/drain region configure a memory transistor. The memorycell MC is comprised of the control transistor and the memorytransistor. That is, the control transistor and the memory transistorshare the source/drain region. A distance between the drain region andthe source region in the gate length direction (X direction) of thecontrol gate electrode CG or the memory gate electrode MG corresponds tothe channel length of the memory cell MC. The control transistor and thememory transistor are each a FINFET having a channel including thesurface of the fin FA.

The control gate electrode CG includes a metal film WF for adjustment ofthe threshold voltage of the control transistor and a metal film M1 onthe metal film WF. The metal film WF covers the bottom and the sidefaces of the metal film M1. The metal film WF includes, for example, aTiAlN film. The metal film M1 is a main conductor film of the controlgate electrode CG, and includes, for example, an aluminum (Al) film or atungsten (W) film. Thus, the control gate electrode CG is formed of themetal films WF and M1 rather than a polysilicon film, and is thusreduced in resistance. When the control gate electrode CG is reduced inresistance in this way, the gate electrode of the memory transistor,which shares a channel with the control transistor, i.e., the memorygate electrode MG must also be reduced in resistance. In the firstembodiment, therefore, part of the memory gate electrode MG is formed ofa metal film M2 as described below.

The memory gate electrode MG includes a polysilicon film PS1, a metalfilm M2, and a polysilicon film PS2 formed in order on the ONO film ON.A material having heat resistance and a relatively low reactivity withsilicon is used as a material of the metal film M2 formed on thepolysilicon film PS1. Specifically, for example, a titanium nitride(TiN) film, a tantalum nitride (TaN) film, or a tungsten nitride (WN)film, which has a lower reactivity with silicon than the aluminum (Al)film or the tungsten (W) film, is used as the metal film M2.

As shown in the right diagram of FIG. 4, the polysilicon film PS1, themetal film M2, and the polysilicon film PS2, which collectively form thememory gate electrode MG, are partially provided below the top of thefin FA. In other words, a trench, which is located on the elementisolation film EI between the two adjacent fins FA, is not completelyfilled only with the ONO film ON and the polysilicon film PS1.Furthermore, the trench is not completely filled only with the ONO filmON, the polysilicon film PS1, and the metal film M2.

Specifically, the trench between the two fins FA is completely filledwith the ONO film ON, the polysilicon film PS1, the metal film M2, andthe polysilicon film PS2. The completely filled state as referred toherein means a state in which the entire region between the adjacentfins FA is filled with a predetermined film. Hence, part of the top ofeach of the ONO film ON, the polysilicon film PS1, and the metal film M2is located below the top of the fin FA. The polysilicon film PS1 has athickness of, for example, 10 nm, and the metal film M2 has a thicknessof, for example, 5 nm.

A height of the fin FA protruding above the element isolation film EI,i.e., a distance from the top of the fin FA to the top of the elementisolation film EI in a direction perpendicular to the main surface ofthe semiconductor substrate SB is, for example, 40 to 60 nm. The totalheight of the fin FA, i.e., the distance from the top of the fin FA tothe bottom of the element isolation film EI in the directionperpendicular to the main surface of the semiconductor substrate SB is,for example, 100 nm or more. A distance between the adjacent fins FA inthe Y direction is, for example, 120 nm. The space between the adjacentfins FA is not completely filled with the ONO film ON, the polysiliconfilm PS1, and the metal film M2. This means that the total thickness ofthe ONO film ON, the polysilicon film PS1, and the metal film M2 is lessthan ½ of the distance between the adjacent fins FA.

The metal film M2 continuously covers the bottom of the polysilicon filmPS2 and the side face of the polysilicon film PS2 on a side close to thecontrol gate electrode CG. In other words, the metal film M2 has anL-shaped section. The polysilicon film PS1 continuously covers thebottoms of the metal film M2 and the polysilicon film PS2 and the sideface of each of the metal film M2 and the polysilicon film PS2 on a sideclose to the control gate electrode CG. In other words, the polysiliconfilm PS1 has an L-shaped section. Hence, the silicon oxide film X1, thesilicon nitride film NF, the silicon oxide film X2, the polysilicon filmPS1, and the metal film M2 are sequentially formed from the side closeto the control gate electrode CG to the side close to the polysiliconfilm PS1.

The tops of the polysilicon film PS1, the metal film M2, and thepolysilicon film PS2 exist at the top of the memory gate electrode MG.In other words, the tops of the polysilicon film PS1, the metal film M2,and the polysilicon film PS2 are in contact with the bottom of theinsulating film IF5.

Subsequently, a structure of a region for power feeding to the memorygate electrode is described with reference to FIGS. 5 and 6. No fin isprovided in the power feeding region shown in FIGS. 5 and 6, and boththe control gate electrode and the memory gate electrode are provided onthe element isolation film in the power feeding region. In the powerfeeding region, the insulating film IF5 (see FIG. 4) on the memory gateelectrode is removed in order to couple the plug to the memory gateelectrode MG. In FIG. 5, each of the control gate electrode CG, thememory gate electrode MG, and the ONO film ON is shown as one film, andthe stacked structure configuring each of the control gate electrode CG,the memory gate electrode MG, and the ONO film ON is not specificallyshown.

As illustrated in FIGS. 5 and 6, in the power feeding region for thememory gate electrode MG, the plug PG is not coupled to the top of thememory gate electrode MG extending in parallel with the control gateelectrode CG, but is coupled to a portion of the memory gate electrodeMG protruding in the X direction from the memory gate electrode MGextending in the Y direction. Since the memory gate electrode MG isformed in a sidewall shape adjacent to the control gate electrode CG, adummy pattern of the control gate electrode CG is provided so as to beadjacent to the memory gate electrode MG extending in the Y direction inorder to allow the memory gate electrode MG to protrude in the Xdirection. Specifically, the control gate electrode CG extending in theY direction and the control gate electrode CG as a dummy pattern areprovided so as to sandwich, in the X direction, the memory gateelectrode MG extending in the Y direction.

The control gate electrode CG as the dummy pattern has an island patternsurrounded by the memory gate electrode MG extending in the Y directionand the memory gate electrode MG as a protrusion, and is a pseudo gateelectrode that does not contribute to formation of a memory cell and acircuit. In this structure, two plugs PG are coupled to the protrudingmemory gate electrode MG. Even if part of the plug is coupled to thecontrol gate electrode CG as the dummy pattern, a problem such as shortcircuit does not occur because the control gate electrode CG does notcontribute to formation of a memory and a circuit.

As illustrated in FIG. 6, the plug PG used for applying a memory gatevoltage to the memory gate electrode MG is directly coupled to the metalfilm M2 forming the memory gate electrode MG. In detail, the top of thememory gate electrode MG includes the tops of the polysilicon film PS1,the metal film M2, and the polysilicon film PS2, and such tops are incontact with the bottom of the plug PG.

Although no silicide layer is provided on the tops of the polysiliconfilms PS1 and PS2, since the plug PG is coupled to the metal film M2,contact resistance between the plug PG and the memory gate electrode MGincluding the metal film M2 can be reduced. Since width of the memorygate electrode in the gate length direction (X direction) is extremelysmall, it may be difficult to form a silicide layer covering a top of amemory gate electrode made of polysilicon only, for example. In thefirst embodiment, however, it is possible to reduce the couplingresistance between the memory gate electrode MG and the plug PG withoutforming the silicide layer.

Operation of Nonvolatile Memory

Exemplary operation of the nonvolatile memory is now described withreference to FIGS. 25 and 26.

FIG. 25 is an equivalent circuit diagram of the memory cell MC of thenonvolatile memory. FIG. 26 is a table showing an example of a conditionof voltage application to each part of a selected memory cell in“write”, “erase”, and “read”. The table of FIG. 26 shows a voltage Vmgapplied to the memory gate electrode MG (see FIG. 4), a voltage Vsapplied to the source region, a voltage Vcg applied to the control gateelectrode CG (see FIG. 4), and a voltage Vd applied to the drain regionof the memory cell (selected memory cell) MC shown in FIG. 25, and avoltage Vb applied to the p-type well PW (see FIG. 4) for each of“write”, “erase”, and “read”. The table shown in FIG. 26 is a preferred,but not limitative, example of the voltage application condition, andcan be variously modified or altered as necessary. In the firstembodiment, injection of electrons into the silicon nitride film NF (seeFIG. 4), which is a charge storage part of the ONO film ON of the memorytransistor, is defined as “write”, and injection of holes thereinto isdefined as “erase”.

Write methods may include a write method called source side injection(SSI) method (hot electron injection write method), in which hotelectrons are injected through source side injection to perform write.For example, a voltage as shown in the column of “write” in FIG. 26 isapplied to each part of the selected memory cell to be written, and thuselectrons are injected into the silicon nitride film NF of the selectedmemory cell to perform write.

At this time, hot electrons are generated in the channel region (betweenthe source and the drain) below between the two gate electrodes (thememory gate electrode MG and the control gate electrode CG), and the hotelectrons are injected into the silicon nitride film NF as a chargestorage part under the memory gate electrode MG. The injected hotelectrons (electrons) are trapped in trap levels in the silicon nitridefilm NF. As a result, the threshold voltage of the memory transistorincreases. That is, the memory transistor becomes into a write state.

An erase method (hot hole injection erase method), i.e., a so-calledBTBT method, in which erase is performed by hot hole injection throughband-to-band tunneling (BTBT), can be used as an erase method.Specifically, erase is performed by injecting holes, which are generatedby the band-to-band tunneling phenomenon (BTBT), into the charge storagepart (the silicon nitride film NF in the ONO film ON). For example, avoltage as shown in the column of “erase” in FIG. 26 is applied to eachpart of the selected memory cell to be erased, and holes are generatedthrough the BTBT phenomenon and accelerated by an electric field,thereby the holes are injected into the silicon nitride film NF of theselected memory cell, so that the threshold voltage of the memorytransistor is reduced. That is, the memory transistor becomes into anerase state.

For read, for example, a voltage as shown in the column of “read” inFIG. 26 is applied to each part of the selected memory cell to be read.A voltage Vmg applied to the memory gate electrode MG during read is setto a value between the threshold voltage of the memory transistor in awrite state and the threshold voltage of the memory transistor in anerase state, thereby the write state can be distinguished from the erasestate.

Manufacturing Process of Semiconductor Device

A method of manufacturing the semiconductor device of the firstembodiment is now described with reference to FIGS. 7 to 24. FIGS. 7 to24 are each a sectional view of the semiconductor device of the firstembodiment during a formation process of the semiconductor device. FIGS.7 to 11 each illustrate a section along the Y direction (see FIG. 2).Each of FIGS. 12 to 24 illustrates a section along the X direction (seeFIG. 2) on its left side and a section along the Y direction on itsright side as with FIG. 4. Although the side face of each fin isvertically shown in the drawings, the side face of the fin may betapered with respect to the main surface of the semiconductor substrate.

First, as illustrated in FIG. 7, the semiconductor substrate SB isprovided, and an insulating film IF1, an insulating film IF2, and asemiconductor film SI1 are formed in order on the main surface of thesemiconductor substrate SB. The semiconductor substrate SB is made ofp-type single-crystal silicon having a specific resistance of about 1 to10 Ωcm, for example. The insulating film IF1 includes, for example, asilicon oxide film, and can be formed by an oxidation process or achemical vapor deposition (CVD) process, for example. The insulatingfilm IF1 has a thickness of about 2 to 10 nm. The insulating film IF2includes, for example, a silicon nitride film, and has a thickness ofabout 20 to 100 nm. The insulating film IF2 is formed by a CVD process,for example. The semiconductor film SI1 includes, for example, a siliconfilm, and is formed by a CVD process, for example. The semiconductorfilm SI1 has a thickness of 20 to 200 nm, for example.

Subsequently, the semiconductor film SI1 is processed using aphotolithography technique and an etching process. Consequently, aplurality of patterns of the semiconductor film SI1 extending in the Xdirection are formed side by side in the Y direction on the insulatingfilm IF2. FIG. 7 is a sectional view including the patterns of thesemiconductor film SI1 along a short side direction of each pattern ofthe semiconductor film SI1.

Subsequently, as illustrated in FIG. 8, a hard mask HM1 is formed so asto cover the side faces of the semiconductor films SI1. For example, asilicon oxide film having a thickness of 10 to 40 nm is formed on thesemiconductor substrate SB by a CVD process, and is then subjected todry etching being anisotropic etching. As a result, the tops of theinsulating film IF2 and the semiconductor film SI1 are exposed to formthe hard mask HM1 including the silicon oxide film remaining on the sidefaces of the semiconductor films SI1. The hard mask HM1 does notcompletely fill the spaces between the adjacent semiconductor films SI1.The hard mask HM1 is annularly formed so as to enclose eachsemiconductor film SI1.

Subsequently, the semiconductor films SI1 are removed by a wet etchingprocess. Subsequently, part of the hard mask HM1 is removed using aphotolithography technique and an etching process. Specifically,portions of the hard mask HM1, which extend in the X direction, are leftwhile other portions, i.e., portions extending in the Y direction areremoved. Consequently, the hard mask HM1 does not have the annularstructure, and has only patterns extending in the X direction.Specifically, a plurality of hard masks HM1 as patterns extending in theX direction are arranged side by side in the Y direction on theinsulating film IF2.

Subsequently, as illustrated in FIG. 9, the insulating films IF2 and IF1and the semiconductor substrate SB are subjected to anisotropic dryetching using the hard masks HM1 as a mask. Thus, plate-like (wall-like)patterns as part of the semiconductor substrate SB i.e., the fins FA,are formed directly under the hard masks HM1 through processing of thesemiconductor substrate SB. The semiconductor substrate SB in a regionexposed from the hard masks HM1 is dug from its main surface by 100 to250 nm, thereby the fins FA, each of which has a height of 100 to 250 nmfrom the main surface of the semiconductor substrate SB, can be formed.

Subsequently, as illustrated in FIG. 10, an insulating film including asilicon oxide film or the like is deposited on the semiconductorsubstrate SB so as to completely cover the fin FA and the insulatingfilms IF1 and IF2. Subsequently, the insulating film is polished by achemical mechanical polishing (CMP) process to expose the top of theinsulating film IF2. This results in formation of the element isolationfilm EI including the insulating film. The hard masks HM1 are removed bythe CMP step. The hard masks HM1 may be removed before forming theinsulating film to be the element isolation film EI.

Subsequently, as illustrated in FIG. 11, the insulating films IF1 andIF2 are removed. Subsequently, the top of the element isolation film EIis etched so as to be retracted (lowered) in a direction perpendicularto the main surface of the semiconductor substrate SB. This results inexposure of part of each of side faces and the tops of the fins FA.

Subsequently, an impurity is introduced into the main surface of thesemiconductor substrate SB by an ion implantation process, thereby ap-type well PW is formed in the fin FA. The p-type well PW is formed byimplanting a p-type impurity (for example, boron (B)). The p-type wellPW is formed while being spread over the entire inside of the fin FA andover part of the semiconductor substrate SB under the fin FA.

Subsequently, as illustrated in FIG. 12, an insulating film IF3 isformed so as to cover the tops and the side faces of the fins FA. Theinsulating film IF3 can be formed by, for example, a thermal oxidationprocess, and includes a silicon oxide film having a thickness of about 2nm, for example. The insulating film IF3 is not formed on the top of theelement isolation film EI. Subsequently, a semiconductor film SI2 havinga thickness equal to or greater than the height of each fin FA isdeposited on the insulating film IF3 by a CVD process or the like, andthe top of the semiconductor film SI2 is planarized by a CMP process orthe like, thereby the semiconductor film SI2 having a flat top isformed.

Subsequently, an insulating film IF4 is formed on the semiconductor filmSI2 by a CVD process, for example. The semiconductor film SI2 includes,for example, a polysilicon film (silicon film), and the insulating filmIF4 includes, for example, a silicon nitride film. The semiconductorfilm SI2 remains on the tops of the fins FA even after the polishingstep is performed on the semiconductor film SI2 by the CMP process asdescribed above.

Subsequently, as illustrated in FIG. 13, an undepicted photoresist filmis formed so as to cover directly over part of the fin FA. Thephotoresist film includes a resist pattern that extends in the Ydirection so as to cover part of each of the fins FA arranged in the Ydirection (depth direction in the drawing). The top of the fin FA isexposed from the photoresist film in a region beside the resist pattern.

Subsequently, part of the insulating film IF4 and part of thesemiconductor film SI2 are removed by etching using the photoresist filmas a mask to expose the top of the element isolation film EI and thesurface of the insulating film IF3. Specifically, part of the top andpart of the side face of the fin FA is exposed from the insulating filmIF4 and the semiconductor film SI2. Consequently, a dummy gate electrodeDG1 including the semiconductor film SI2 is formed on the fin FA. Thedummy gate electrode DG1 is a pseudo gate electrode that is removedlater and replaced with a control gate electrode.

Although it is described that the insulating film IF3 covering thesurface of the fin FA exposed from the dummy gate electrode DG1 isremoved by the above-described etching and a subsequent cleaning step toexpose the surface of the fin FA, the top and the side faces of the finFA may be still covered with the insulating film IF3.

Subsequently, as illustrated in FIG. 14, a silicon oxide film (bottomoxide film) X1, a silicon nitride film NF, and a silicon oxide film (topoxide film) X2 are formed in order on the semiconductor substrate SB,thereby the ONO film ON having a stacked structure including the siliconoxide film X1, the silicon nitride film NF, and the silicon oxide filmX2 is formed. That is, the ONO film ON is a stacked insulating film. Thesilicon oxide film X1 can be formed by an oxidation process, a CVDprocess, or the like. The silicon nitride film NF and the silicon oxidefilm X2 are formed (deposited) by a CVD process, for example. Thesilicon oxide film X1 has a thickness of, for example, 4 nm, the siliconnitride film NF has a thickness of, for example, 7 nm, and the siliconoxide film X2 has a thickness of, for example, 9 nm.

The ONO film ON covers the top of the element isolation film EI as wellas the top and the side face of the fin FA. The ONO film ON covers thetop and the side face of the stacked pattern including the dummy gateelectrode DG1 and the insulating film IF4. Although the silicon nitridefilm NF serves as a charge storage part (charge storage film) of amemory cell to be formed later, a high-k film including HfSiO or thelike may be formed instead of the silicon nitride film NF. An aluminumoxide (A10) film may be formed instead of the silicon oxide film X2.

Subsequently, the polysilicon film PS1, the metal film M2, and thepolysilicon film PS2 are formed in order on the ONO film ON. Thepolysilicon film PS1 has a thickness of, for example, 10 nm, the metalfilm M2 has a thickness of, for example, 5 nm, and the polysilicon filmPS2 has a thickness of, for example, 200 nm. Subsequently, the top ofthe polysilicon film PS2 is planarized by a CMP process, for example.However, the metal film M2 is not exposed from the polysilicon film PS2in the planarization step. Hence, the polysilicon film PS2 is providedon the fin FA with the ONO film ON, the polysilicon film PS1, and themetal film M2 in between.

At this time, a region between the fins FA adjacent to each other in theY direction, i.e., the trench over the element isolation film EI iscompletely filled with the ONO film ON, the polysilicon film PS1, themetal film M2, and the polysilicon film PS2. The polysilicon films PS1and PS2 can each be formed by a CVD process. The metal film M2 can beformed by a sputtering process, for example.

A material having heat resistance and a relatively low reactivity withsilicon is used as a material of the metal film M2. Specifically, atitanium nitride (TiN) film, a tantalum nitride (TaN) film, or atungsten nitride (WN) film, which has a lower reactivity with siliconthan the aluminum (Al) film or the tungsten (W) film, is used as themetal film M2. This prevents the metal film M2 from reacting with thepolysilicon film PS1 or PS2.

Subsequently, as illustrated in FIG. 15, the tops of the ONO film ON,the polysilicon film PS1, the metal film M2, and the polysilicon filmPS2 are retracted by an etch-back step. As a result, each of the tops ofthe ONO film ON, the polysilicon film PS1, the metal film M2, and thepolysilicon film PS2 is located at a position below the top of the dummygate electrode DG1 and above the top of the metal film M2 along the topof the fin FA, for example. In addition, the tops of the ONO film ON,the polysilicon film PS1, the metal film M2, and the polysilicon filmPS2 are located at the same height, and exist in substantially the sameplane. Consequently, the entire insulating film IF4 and the upper end ofthe dummy gate electrode DG1 are exposed from the ONO film ON, thepolysilicon film PS1, the metal film M2, and the polysilicon film PS2.

Subsequently, as illustrated in FIG. 16, an insulating film IF5 isformed over the semiconductor substrate SB by a CVD process, forexample. The insulating film IF5 includes, for example, a siliconnitride film. The insulating film IF5 covers the side faces and the topof the insulating film IF4, the upper ends of the side faces of thedummy gate electrode DG1, and the tops of the ONO film ON, thepolysilicon film PS1, the metal film M2, and the polysilicon film PS2.

Subsequently, part of the insulating film IF5 is removed by dry etchingto expose the top of the insulating film IF4 and part of the top of thepolysilicon film PS2. That is, the insulating film IF5 remains on theside faces of the insulating film IF4 in a sidewall shape. The bottom ofthe sidewall-shaped insulating film IF5 is in contact with the tops ofthe ONO film ON, the polysilicon film PS1, the metal film M2, and thepolysilicon film PS2.

Subsequently, as illustrated in FIG. 17, the ONO film ON, thepolysilicon film PS1, the metal film M2, and the polysilicon film PS2are processed by etching using the insulating film IF5 as a mask.Consequently, the ONO film ON, the polysilicon film PS1, the metal filmM2, and the polysilicon film PS2 remain in a region close to the sideface on either side of the dummy gate electrode DG1. The top of the finFA is exposed from the ONO film ON, the polysilicon film PS1, the metalfilm M2, and the polysilicon film PS2 in any region other than theregion close to the side face on either side of the dummy gate electrodeDG1.

The polysilicon film PS1, the metal film M2, and the polysilicon filmPS2 are close to one side face in the gate length direction (Xdirection) of the dummy gate electrode DG1 with the ONO film ON inbetween, and collectively configure the memory gate electrode MG. Thememory gate electrode MG extends in the Y direction so as to straddlethe fins FA in parallel with the dummy gate electrode DG1.

Subsequently, as illustrated in FIG. 18, an undepicted resist pattern,which covers the memory gate electrode MG and the insulating film IF5directly over the memory gate electrode MG, is formed, and then theinsulating film IF5, the ONO film ON, the polysilicon film PS1, themetal film M2, and the polysilicon film PS2 exposed from the resistpattern are removed by etching using the resist pattern as a mask.Consequently, the memory gate electrode MG remains in the gate lengthdirection on one side face of the dummy gate electrode DG1 with the ONOfilm ON in between, and the other side face of the dummy gate electrodeDG1 is exposed from the ONO film ON, the polysilicon film PS1, the metalfilm M2, and the polysilicon film PS2.

Subsequently, as illustrated in FIG. 19, the insulating films IF4 andIF5 and the dummy gate electrode DG1 are collectively used as a mask toperform ion implantation on the top of the fin FA. Consequently, a pairof extension regions EX being n-type semiconductor regions are formed inthe top of the fin FA. The extension region EX can be formed byimplanting an n-type impurity (for example, arsenic (As).

Subsequently, an insulating film is formed over the semiconductorsubstrate SB by a CVD process, for example. The insulating film mainlyincludes, for example, a silicon nitride film. The insulating filmcovers the surfaces of the element isolation film EI, the fin FA, thedummy gate electrode DG1, the memory gate electrode MG, and theinsulating films IF4 and IF5.

Subsequently, as illustrated in FIG. 20, dry etching is performed toremove part of the insulating film, thereby the tops of the elementisolation film EI, the fin FA, and the insulating films IF4 and IF5 areexposed. The sidewall SW including the insulating film is thus formed onthe side face of a pattern including the dummy gate electrode DG1, thememory gate electrode MG, and the insulating films IF4 and IF5.

Subsequently, ion implantation is performed on the top of the fin FAwith a mask including the insulating films IF4 and IF5, the dummy gateelectrode DG1, and the sidewall SW. An n-type impurity (for example,phosphorus (P) or arsenic (As)) is implanted, thereby a pair ofdiffusion regions D1 each being an n-type semiconductor region areformed in the top of the fin FA. In the formation step of the diffusionregion D1, ion implantation is performed with an impurity concentrationhigher than that in the ion implantation step for formation of theextension region EX. Subsequently, heat treatment for activation isperformed in order to diffuse the impurity in the semiconductorsubstrate SB. As a result, the impurity contained in the diffusionregion D1, the extension region EX, and the like are thermally diffused.

Consequently, the source/drain region including the diffusion regions D1and the extension regions EX is formed. The source/drain region isformed in the top and the side face of the fin FA exposed from a patternincluding the control gate electrode CG and the memory gate electrodeMG, i.e., in the surface of the fin FA. The source/drain region and thememory gate electrode MG configure a memory transistor. The memorytransistor is a FINFET having a channel including the surface of the finFA. The surface of the fin FA as referred to herein includes the top andthe side face of the fin FA.

Subsequently, as illustrated in FIG. 21, a silicide layer is formed soas to cover the source/drain region using a known salicide (self alignsilicide) process. First, a metal film is formed so as to cover the finFA. The metal film includes, for example, a NiPt film deposited by asputtering process. Subsequently, heat treatment is performed on thesemiconductor substrate SB to react the surface of the fin FA with themetal film. This results in formation of the silicide layer S1 includinga nickel silicide (NiSi) film covering the top and a side face of thediffusion region D1.

Subsequently, an undepicted liner film including, for example, a siliconnitride film and the interlayer insulating film IL1 including a siliconoxide film are formed in order over the main surface of thesemiconductor substrate SB. The liner film and the interlayer insulatingfilm IL1 can be formed by a CVD process, for example. The interlayerinsulating film IL1 has a thickness larger than the total height of theheight of the fin FA on the element isolation film EI and the height ofa stacked body including the dummy gate electrode DG1 and the insulatingfilm IF4. Subsequently, the top of the interlayer insulating film IL1 isplanarized using a CMP process, for example.

In this planarization step, the insulating film IF4 is entirely removed,and the insulating film IF5 is partially removed, thereby the top of thedummy gate electrode DG1 is exposed. In the planarization step, however,the tops of the ONO film ON, the polysilicon film PS1, the metal filmM2, and the polysilicon film PS2 are not exposed. That is, the tops ofthe ONO film ON, the polysilicon film PS1, the metal film M2, and thepolysilicon film PS2 are still covered with the insulating film IF5 evenafter the planarization step.

Subsequently, as illustrated in FIG. 22, the dummy gate electrode DG1including a polysilicon film is removed by wet etching, for example. Asa result, a trench is formed in a region, from which the dummy gateelectrode DG1 is removed, on the directly over the insulating film IF3.

While the silicon film is selectively removed in this step, thepolysilicon films PS1 and PS2 are covered with the insulating film IF5and are thus not removed. Specifically, since the tops of the ONO filmON, the polysilicon film PS1, the metal film M2, and the polysiliconfilm PS2 are retracted below with respect to the top of the dummy gateelectrode DG1 in the etch-back step described with reference to FIG. 15,it is possible to prevent the memory gate electrode MG protected by theinsulating film IF5 from being removed by the wet etching.

Subsequently, as illustrated in FIG. 23, the control gate electrode CGis formed in that trench. Specifically, first, the highdielectric-constant film HK, the metal film WF, and the metal film M1are formed in order on the interlayer insulating film IL1 including theinside of the trench, thereby the trench is completely filled with thehigh dielectric-constant film HK, the metal film WF, and the metal filmM1. Subsequently, the excess high dielectric-constant film HK, metalfilm WF, and metal film M1 on the interlayer insulating film IL1 areremoved using, for example, a CMP process to expose the top of theinterlayer insulating film IL1. Consequently, the highdielectric-constant film HK, the metal film WF, and the metal film M1are left in the trench.

The insulating film IF3 and the high dielectric-constant film HKconfigure the gate insulating film. The metal films WF and M1 configurethe control gate electrode CG. The control gate electrode CG and thesource/drain region configure the control transistor. The controltransistor and the memory transistor configure the memory cell MC. Thecontrol transistor is a FINFET having a channel including the surface ofthe fin FA. The surface of the fin FA as referred to herein includes thetop and the side faces of the fin FA.

Subsequently, as illustrated in FIG. 24, a plurality of contact holespenetrating through the interlayer insulating films IL1 and IL2 areformed by a photolithography technique and a dry etching process. Thetop of the silicide layer S1 directly over the source/drain region ispartially exposed on the bottom of the contact hole. Contact holes areformed in undepicted regions so as to partially expose the respectivetops of the control gate electrode CG and the memory gate electrode MG.

Subsequently, a conductive plug PG mainly made of tungsten (W) or thelike is formed as a coupling conductive component in the contact holeCH. The plug PG has a stacked structure of a barrier conductor film (forexample, a titanium film, a titanium nitride film, or a stacked filmthereof) and a main conductor film (for example, tungsten film) locatedon the barrier conductor film. The plug PG is electrically coupled toeach of the source and drain regions of the memory cell MC via thesilicide layer S1.

Subsequently, the interconnections MW are formed on the interlayerinsulating film IL2. Each interconnection MW includes a stackedstructure of a barrier conductor film (for example, a titanium nitridefilm, a tantalum film, or a tantalum nitride film) and a main conductorfilm (copper film) formed on the barrier conductor film. In FIG. 24, thebarrier conductor film and the main conductor film forming theinterconnection MW are shown in an integrated manner for simplificationof the drawing. The same point is valid with regard to the plug PG. Thesemiconductor device of the first embodiment is substantially completedthrough the above-described steps.

The interconnection MW can be formed by, for example, a so-called singledamascene process. Specifically, an interlayer insulating film having aninterconnection trench is formed on the interlayer insulating film IL2,and a metal film is embedded in the interconnection trench, thereby theinterconnection MW can be formed. In the drawing, however, theinterlayer insulating film beside the interconnection MW is omitted.

Effects of First Embodiment

Effects of the semiconductor device of the first embodiment is nowdescribed with reference to comparative examples shown in FIGS. 33 to35. FIGS. 33 to 35 are each a sectional view of a semiconductor deviceof the comparative example. FIGS. 33 to 35 each illustrate crosssections at positions corresponding to those of the cross sections shownin FIG. 4, which each show a cross section of a memory cell along alongitudinal direction of a fin and a cross section of the memory cellalong a lateral direction of the fin.

The semiconductor device of the comparative example shown in FIG. 33 isdifferent from the semiconductor device of the first embodiment in thata memory gate electrode MG1 is entirely formed only of a polysiliconfilm. The semiconductor device of the comparative example shown in FIG.34 is different from the semiconductor device of the first embodiment inthat a memory gate electrode MG2 is entirely formed of a metal film (forexample, aluminum (Al) or tungsten (W) film). Although the semiconductordevice of the comparative example shown in FIG. 35 includes a memorygate electrode MG3 formed of a polysilicon film PSB and a metal film MBon the polysilicon film PSB, the semiconductor device is different fromthe semiconductor device of the first embodiment in that the polysiliconfilm PSB has a large thickness, and completely fills a space between twoadjacent fins FA.

In the semiconductor device shown in FIG. 33, since the memory gateelectrode MG1 is formed only of the polysilicon film, the memory gateelectrode MG1 disadvantageously has a high resistance value. Even ifonly the top of the memory gate electrode MG1 is silicided, since thepolysilicon film covering the side faces of the fin FA has highresistance, electric potential is slowly propagated to the lower part ofthe fin FA, leading to a reduction in speed of write or erase.

On the other hand, as illustrated in FIG. 34, when the memory gateelectrode MG2 is entirely formed of a metal film, although the memorygate electrode MG2 has a low resistance, an insulating film (forexample, a silicon oxide film or an aluminum oxide film) between thesilicon nitride film NF as a charge storage film and the memory gateelectrode MG2 may react with that metal film, leading to a possibilityof formation of a metal oxide film. That is, the silicon oxide film X2as the top oxide film of the ONO film ON may react with the metal film.In particular, the memory gate electrode MG2 formed of an aluminum film,a tungsten film, or the like easily reacts with the top oxide film. Whenthe top oxide film becomes a metal oxide film in this way, interfacialcharacteristics between the ONO film ON and the memory gate electrodeMG2 are deteriorated as compared with the case where the memory gateelectrode is entirely formed of a polysilicon film (see FIG. 33).

In such a case, electrons (charges) injected into the ONO film ON bywrite operation are disadvantageously captured in an unintended place,or easily escape from the ONO film ON. In other words, writecharacteristics and charge retention characteristics are deteriorated.Consequently, reliability of the semiconductor device is deteriorated.

On the other hand, in the semiconductor device of the comparativeexample shown in FIG. 35, part of the memory gate electrode MG3 isformed of the metal film MB, and thus resistance of the memory gateelectrode MG3 is reduced. In addition, since the polysilicon film PSB isinterposed between the metal film MB and the ONO film ON, it is possibleto prevent the top oxide film from reacting with the metal unlike theabove-described case.

In the comparative example shown in FIG. 35, however, the metal film MBis not provided between the adjacent fins FA. Hence, electric potentialis still slowly propagated to the lower part of the fin FA due to thehigh resistance of the polysilicon film covering the side faces of thefin FA, and thus write or erase speed is disadvantageously low.

In the first embodiment, therefore, as illustrated in FIG. 4, there isprovided the memory gate electrode MG having the thin polysilicon filmPS1 formed on the ONO film ON and the metal film M2 on the polysiliconfilm PS1. Thus, part of the memory gate electrode MG is formed of themetal film M2, thereby the resistance of the memory gate electrode MG isreduced. In addition, since the polysilicon film PS1 is interposedbetween the metal film M2 and the ONO film ON, it is possible to preventthe top oxide film from reacting with a metal unlike the above-describedcase.

Furthermore, in the first embodiment, the polysilicon film PS1 as thelowermost layer of the memory gate electrode MG having the stackedstructure does not fill the entire trench between the adjacent fins FA,and the metal film M2 is embedded in the trench. Specifically, alow-resistance metal film M2 is provided adjacent to the side face ofthe fin FA, in which the channel of each of the control transistor andthe memory transistor is provided, with the ONO film ON and thepolysilicon film PS1 in between. This makes it possible to reduce theresistance of the memory gate electrode MG in the vicinity of the sideface of the fin FA. It is therefore possible to prevent the electricpotential from being slowly propagated to the lower part of the fin FA.That is, the write operation and the erase operation can be performed ata higher speed than the comparative examples shown in FIGS. 33 and 34.

It is therefore possible to prevent deterioration in reliability of thesemiconductor device due to deterioration in interface characteristicsbetween the ONO film ON and the memory gate electrode MG, and to improveperformance of the semiconductor device by reducing the resistance ofthe memory gate electrode MG.

Further, in the first embodiment, one of the conductive films formingthe memory gate electrode MG, i.e., the conductive film on the metalfilm M2 is formed of the polysilicon film PS2, and the silicide layer isnot formed in the top of the polysilicon film PS2. Even in such a case,the electric potential supplied to the memory gate electrode MG can bepropagated at high speed through the metal film M2. It is thereforepossible to sufficiently reduce the resistance of the memory gateelectrode MG. If the conductive film on the metal film M2 is silicided,or if the conductive film is formed of a metal film, the number ofmanufacturing steps is increased, leading to an increase inmanufacturing cost. On the other hand, the conductive film on the metalfilm M2 is formed of the polysilicon film PS2 in the first embodiment,thereby the manufacturing process can be simplified and themanufacturing cost can be reduced.

Further, as described with reference to FIGS. 5 and 6, since the plug PGis directly coupled to the metal film M2 in the power feeding region forthe memory gate electrode MG, even if the surface of the polysiliconfilm PS2 is not silicided, the coupling resistance between the memorygate electrode MG and the plug PG can be reduced.

Modification

A modification of the semiconductor device of the first embodiment isnow described with reference to FIG. 27. FIG. 27 is a sectional viewillustrating a semiconductor device as a modification of the firstembodiment. FIG. 27 shows a cross section of a power feeding region forthe memory gate electrode. FIG. 27 shows a cross section along thelateral direction of the fin. This modification is different from thesemiconductor device described with reference to FIGS. 1 to 24 only inthe mode of the plug coupled to the memory gate electrode.

As illustrated in FIG. 27, the plug PG used for power feeding to thememory gate electrode MG is not necessary to be coupled to the top ofthe entire stacked film including the polysilicon film PS1, the metalfilm M2, and the polysilicon film PS2, and may be coupled to the top ofthe metal film M2 while penetrating through the polysilicon film PS2. Inother words, the plug PG penetrates through the interlayer insulatingfilm IL2 and the polysilicon film PS2, and is coupled to the top of themetal film M2 under the polysilicon film PS2.

The entire bottom of the plug PG is coupled to the top of the metal filmM2 extending in the X direction and the Y direction along the mainsurface of the semiconductor substrate SB and along the top of theelement isolation film EI. In such a case, the contact area between theplug PG and the metal film M2 can be increased as compared with thestructure shown in FIG. 6. Hence, this modification provides the effectssimilar to those of the semiconductor device described with reference toFIGS. 1 to 24, and makes it possible to further reduce the couplingresistance between the plug PG and the memory gate electrode MG.

Second Embodiment

The top of the polysilicon film forming the memory gate electrode canalso be silicided. A semiconductor device and a method of manufacturingthe semiconductor device according to a second embodiment is nowdescribed with reference to FIGS. 28 to 30. FIGS. 28 to 30 are each asectional view of the semiconductor device of the second embodimentduring a manufacturing process of the semiconductor device. FIGS. 28 to30 show respective cross sections at positions corresponding to those ofthe cross sections shown in FIGS. 12 to 24, which each show a crosssection of a memory cell along the longitudinal direction of the fin anda cross section of the memory cell along the lateral direction of thefin. Silicidation of the top of the polysilicon film forming the memorygate electrode is now described.

First, steps similar to those described with reference to FIGS. 7 to 23are performed. Subsequently, as illustrated in FIG. 28, part of theinsulating film IF5 is removed by a photolithography technique and anetching process to expose the top of the polysilicon film PS2. At thistime, the metal film M2 is not exposed. Although not shown in thedrawing, a protective film covering the top of the control gateelectrode CG including the metal films WF and M1 is formed before theinsulating film IF5 is partially removed by etching as described above,and while the control gate electrode CG is covered with the protectivefilm, a silicide layer formation step is performed as follows.

Subsequently, as illustrated in FIG. 29, the top of the polysilicon filmPS2 is silicided using a known salicide process, thereby a silicidelayer S2 covering the top of the polysilicon film PS2 is formed. Thatis, a metal film covering the top of the polysilicon film PS2 is formed.The metal film includes, for example, a NiPt film deposited by asputtering process. Subsequently, heat treatment is performed on thesemiconductor substrate SB to react the polysilicon film PS2 with themetal film. This results in formation of the silicide layer S2 includinga nickel silicide (NiSi) film covering the top of the polysilicon filmPS2.

Subsequently, as illustrated in FIG. 30, steps similar to thosedescribed with reference to FIG. 24 are performed, thereby thesemiconductor device of the second embodiment is substantiallycompleted. Although it has been described that a part of the polysiliconfilm PS2 is left and the silicide layer S2 is formed on the part of thepolysilicon film PS2, the entire thickness of the polysilicon film PS2may be silicided. That is, the bottom of the silicide layer S2 may be incontact with the top of the metal film M2 as with a metal film M3 shownin FIG. 32 used in later description. In such a case, the silicide layerS2 is embedded between the adjacent fins FA.

In the second embodiment, since the top of the polysilicon film PS2 issilicided, the resistance of the memory gate electrode MG can be reducedas compared with the case where the entire conductive film on the metalfilm M2 is formed of a polysilicon film. In addition, when the plug iscoupled to the memory gate electrode MG in the power feeding region forthe memory gate electrode MG, since the plug PG can be coupled to thesilicide layer S2, the coupling resistance between the plug PG and thememory gate electrode MG can be reduced.

Hence, it is possible to reduce the resistance of the entire memory gateelectrode MG by forming the low-resistance metal film M2 in the vicinityof each side face of the fin FA. Furthermore, performance of thesemiconductor device can be improved by performing silicidation of thepolysilicon film PS2.

Third Embodiment

The memory gate electrode can also be configured only of a polysiliconfilm and a metal film on the polysilicon film. A semiconductor deviceand a method of manufacturing the semiconductor device according to athird embodiment is now described with reference to FIGS. 31 and 32.FIGS. 31 and 32 are each a sectional view of the semiconductor device ofthe third embodiment during a manufacturing process of the semiconductordevice. FIGS. 31 and 32 show respective cross sections at positionscorresponding to those of the cross sections shown in FIGS. 12 to 24,which each show a cross section of a memory cell along the longitudinaldirection of the fin and a cross section of the memory cell along thelateral direction of the fin. It is now described that the memory gateelectrode is formed of a polysilicon film and a stacked metal film onthe polysilicon film.

First, steps similar to those described with reference to FIGS. 7 to 23and 28 are performed. Subsequently, as illustrated in FIG. 31, theentire polysilicon film PS2 is removed using an etching process. As aresult, a trench is formed at a position where the polysilicon film PS2has been provided, and the top of the metal film M2 is exposed on thebottom and on one side face of the trench. The control gate electrode CGcovered with the above-described protective film (not shown) is notremoved.

Subsequently, as illustrated in FIG. 32, the metal film M3 is formed by,for example, a sputtering process on the main surface of thesemiconductor substrate SB including the inside of the trench. The metalfilm M3 is thus embedded in the trench. Subsequently, the excess metalfilm M3 on the interlayer insulating film IL1 is removed by, forexample, a CMP process, so that the metal film M3 is left only in thetrench. This results in formation of the memory gate electrode MGincluding a stacked film of the polysilicon film PS1, the metal film M2,and the metal film M3.

The metal film M3 includes, for example, an aluminum (Al) film or atungsten (W) film. Since the metal film M3 is not in contact with thepolysilicon film PS1, it is not necessary to use a material having arelatively low reactivity with silicon as the material of the metal filmM3. It is therefore possible to reduce the resistance of the metal filmM3 as compared with the case where titanium nitride (TiN) or the like,which is a material having a relatively low reactivity with silicon, isused as a material of the metal film M3.

Subsequently, steps similar to those described with reference to FIG. 24are performed, thereby the semiconductor device of the third embodimentis substantially completed.

In the third embodiment, the memory gate electrode MG is formed of thepolysilicon film PS1, the metal film M2, and the metal film M3 formed inorder from the bottom. In the third embodiment, therefore, it ispossible to reduce the resistance of the memory gate electrode MG ascompared with the case where the memory gate electrode MG is formed ofthe stacked film including the polysilicon film PS1, the metal film M2,and the polysilicon film PS2 formed in order from the bottom.

It is therefore possible to reduce the resistance of the entire memorygate electrode MG by forming the low-resistance metal films M2 and M3 inthe vicinity of the side face of the fin FA. Further, a proportion ofthe metal film forming the memory gate electrode MG is increased toreduce the resistance of the memory gate electrode MG, therebyperformance of the semiconductor device can be improved. Even if part ofthe memory gate electrode MG is thus formed of the metal films M2 andM3, since the polysilicon film PS1 is interposed between the metal filmsM2 and M3 and the ONO film ON, it is possible to prevent the top oxidefilm from reacting with the metal unlike the comparative exampledescribed with reference to FIG. 34.

Although the invention achieved by the inventors has been described indetail according to some embodiments thereof hereinbefore, the inventionshould not be limited thereto, and it will be appreciated that variousmodifications or alterations thereof may be made within the scopewithout departing from the gist of the invention.

In the steps described with reference to FIGS. 22 and 23, the dummy gateelectrode DG1 (see FIG. 21) is replaced with a metal film, and thecontrol gate electrode CG including the metal film is formed. On theother hand, the steps described with reference to FIGS. 22 and 23 maynot be performed while the gate electrode including the semiconductorfilm SI2 (see FIG. 12) is formed as the control gate electrode CG ratherthan the dummy gate electrode DG1, and is used as the control gateelectrode CG configuring the memory cell MC.

1-12. (canceled)
 13. A method of manufacturing a semiconductor device,the method comprising the steps of: (a) providing a semiconductorsubstrate; (b) retracting a part of a top of the semiconductorsubstrate, thereby forming a plurality of protrusions that are each aportion of the semiconductor substrate, protrude from the part of thetop of the semiconductor substrate, and extend in a first directionalong the top of the semiconductor substrate; (c) forming an elementisolation film that fills a first trench between the protrusionsadjacent to each other; (d) forming a first gate electrode that coverstops and side faces of the protrusions with a first insulating film inbetween over the element isolation film; (e) after the step (d), forminga second insulating film as a charge storage part, a first semiconductorfilm, and a first metal film in order over the semiconductor substrate,thereby filling a space between the protrusions arranged in a seconddirection orthogonal to the first direction with a stacked filmincluding the first semiconductor film and the first metal film; (f)processing the stacked film to form a second gate electrode includingthe stacked film that is adjacent to one side face of the first gateelectrode with the second insulating film in between, and covers thetops and the side faces of the protrusions with the second insulatingfilm in between; and (g) forming source and drain regions in a surfaceof each of the protrusions beside a pattern including the first gateelectrode and the second gate electrode.
 14. The method according toclaim 13, wherein in the step (e), the second insulating film, the firstsemiconductor film, the first metal film, and a second semiconductorfilm are formed in order over the semiconductor substrate, thereby thespace between the protrusions arranged in the second direction is filledwith a stacked film including the first semiconductor film, the firstmetal film, and the second semiconductor film; the method furthercomprising the step of: (h) after the step (g), siliciding a top of thesecond semiconductor film.
 15. The method according to claim 13, whereinin the step (e), the second insulating film, the first semiconductorfilm, the first metal film, and a second semiconductor film are formedin order over the semiconductor substrate, thereby the space between theprotrusions arranged in the second direction is filled with the stackedfilm including the first semiconductor film, the first metal film, andthe second semiconductor film, the method further comprising the stepsof: (h) after the step (g), removing the second semiconductor film toform a second trench over the second insulating film; and (i) after thestep (h), filling the second trench with a second metal film.